In an information processing device, it is known to detect an error in data which is transferred on a bus as an information transfer path using the ECC code. The error in the data is detected, for example, using a data processing circuit. In detection of an error in data, in the case that the number of bits in data from which an error is to be detected is small, the time taken to transmit the data in the data processing circuit is short. As described above, the time taken to be transmit the data in the data processing circuit is short in the case that the number of bits included in the data concerned is small. Therefore, the time taken for processing the data has not been so increased.
However, with the recent increase in throughput of a central processing unit, the number of bits included in data from which an error is to be detected is increased. The configuration of the data processing circuit used is more complicated with increasing the number of bits included in data concerned. For example, in the case that a gate circuit is used in the data processing circuit, the number of bits which are included in data to be simultaneously processed is increased. Therefore, it may be unavoidable to multi-stage the gate circuit (to have a multi-stage structure). Then, the time taken to transmit the data in the data processing circuit is increased with multi-staging the gate circuit.
In addition, with the above mentioned increase in throughput of the central processing unit, the operating frequency of the central processing unit is increased accordingly. The time of one clock cycle is reduced with increasing the operating frequency. The timing at which the data processing circuit transmits data is delayed with reducing the time of one clock cycle. A hold circuit that holds data is installed in the data processing circuit in order to cope with an increase in operating frequency of the central processing unit. Preferably, the hold circuit includes, for example, a flip flop. The holding circuit is configured to adjust timings at which data is detected and the data is transmitted in the data processing circuit. Therefore, the hold circuit may prevent the timing at which the data is transmitted from being delayed.
However, in many cases, any error does not occur in data which is checked using the data processing circuit. The data is checked regardless of the fact that in many cases any error does not occur in the data. Therefore, excessive time is wasted until a result of error detection is obtained using the data processing circuit.    [Patent Document 1] Japanese Laid-open Patent Publication No. 56-129952    [Patent Document 2] Japanese Laid-open Patent Publication No. 48-63644